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1 ? fn9107.3 caution: these devices are sensitive to electrosta tic discharge; follow proper ic handling procedures. 1-888-intersil or 1-888-468-3774 | intersil (and design) is a registered trademark of intersil americas inc. copyright intersil americas inc. 2004, 2005. all rights reserved all other trademarks mentioned are the property of their respective owners. isl6217a precision multi-phase buck pwm controller for intel, mobile voltage positioning imvp-i v? and imvp-iv+? the isl6217a multi-phase buck pwm controller ic, with integrated half bridge gate drivers, provides a precision voltage regulation system for advanced pentium iv microprocessors in notebook computers. two-phase operation eases the thermal management issues and load demand of intel?s latest high performance processors. this control ic also features both input voltage feed-forward and average current mode control for excellent dynamic response, ?loss-less? current sensing using mosfet r ds(on) and user-selectable switching frequencies from 250khz to 1mhz per phase. the isl6217a includes a 6-bit digital-to-analog converter (dac) that dynamically adjusts the core pwm output voltage from 0.700v to 1.708v in 16mv steps and conforms to the intel imvp-iv? and imvp-iv+? mobile vid specification. the isl6217a also has logic inputs to select active, deep sleep and deeper sleep modes of operation. a precision reference, remote sensing and proprietary architecture, with integrated, processor-mode, compensated ?droop?, provide excellent static and dynamic core voltage regulation. to improve efficiency at light loading, the isl6217a can be configured to run in single phase pwm in active, deep or deeper sleep modes of operation. also, in deep and deeper sleep modes the isl6217a will operate in diode emulation. another feature of this ic c ontroller is the pgood monitor circuit that is held low until core voltage increases, during its soft-start sequence, to wit hin 12% of the ?boot? voltage. this pgood signal is masked during vid changes. output overcurrent, overvoltage and undervoltage are monitored and result in the converter latching off and pgood signal being held low. the overvoltage and undervoltage thresholds are 112% and 84% of the vid, deep or deeper sleep setpoint, respectively. overcurrent protection features a 32 cycle overcurrent shutdown. pgood, overvoltage, undervoltage and overcurrent provide monitoring and protection for the microprocessor and power syst em. the isl6217a ic is available in a 38 lead tssop. features ? diode emulation functionality in deep and deeper sleep modes for improved light load efficiency ? imvp-iv? and imvp-iv+? compliant core regulator ? single and/or two-phase power conversion ? ?loss-less? current sensing for improved efficiency and reduced board area - optional discrete precision current sense resistor ? internal gate-drive and boot-strap diodes ? precision core voltage regulation - 0.8% system accuracy over temperature ? 6-bit microprocessor voltage identification input ? programmable ?droop? and core voltage slew rate to comply with imvp-iv? and imvp-iv+? specification ? direct interface with system logic (stp_cpu# and dprslpvr) for deep and deeper sleep modes of operation ? easily programmable voltage setpoints for initial ?boot?, deep sleep and deeper sleep modes ? excellent dynamic response - combined voltage feed-forward and average current mode control ? overvoltage, undervoltage and overcurrent protection ? power-good output with internal blanking during vid and mode changes ? user programmable switching frequency of 250khz - 1mhz per phase ? pb-free plus anneal available (rohs compliant) data sheet june 30, 2005
2 fn9107.3 june 30, 2005 pinout isl6217a (38 ld tssop) top view ordering information part number temp (c) package pkg. dwg. # isl6217acv -10 to 85 38 ld tssop m38.173 ISL6217ACV-T 38 ld tssop tape and reel m38.173 isl6217acvz (note 1) -10 to 85 38 ld tssop (pb-free) m38.173 isl6217acvz-t (note 1) 38 ld tssop tape and reel (pb-free) m38.173 isl6217acvza -10 to 85 38 ld tssop (pb-free) m38.173 isl6217acvza-t 38 ld tssop tape and reel (pb-free) m38.173 note: intersil pb-free plus anneal products employ special pb-free material sets; molding compounds/die attach materials and 100% matte tin plate termination finish , which are rohs compliant and compatible with both snpb and pb-free soldering operations. intersil pb-free products are msl classi fied at pb-free peak reflow temperatures that meet or exceed the pb-free requirements of ipc/jedec j std-020. 13 1 2 3 4 5 6 7 8 9 10 11 12 14 15 16 17 18 19 vdd dacout dsv fset pwrch en drsen dsen# vid0 vid1 vid2 vid3 vid4 vid5 pgood ea+ comp fb soft 26 38 37 36 35 34 33 32 31 30 29 28 27 25 24 23 22 21 20 vbat isen1 phase1 ug1 boot1 vssp1 lg1 vddp lg2 vssp2 boot2 ug2 phase2 isen2 vsen drsv stv ocset vss isl6217a tssop isl6217a
3 fn9107.3 june 30, 2005 absolute voltage ratings supply voltage, vdd, vddp . . . . . . . . . . . . . . . . . . . . . . . . -0.3-+7v battery voltage, vbat . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .+25v boot1,2 and ugate1,2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .+35v phase1,2 and isen1,2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .+30v boot1,2 with respect to phase1,2 . . . . . . . . . . . . . . . . . . . . . . +6.5v ugate1,2 . . . . . . . . . . . . . . . (phase1,2 - 0.3v) to (boot1,2 + 0.3v) all other pins . . . . . . . . . . . . . . . . . . . . . . . . . -0.3v to (vdd + 0.3v) recommended operating conditions supply voltage, vdd, vddp . . . . . . . . . . . . . . . . . . . . . . . +5v 5% ambient temperature. . . . . . . . . . . . . . . . . . . . . . . . . .-10c to 85c junction temperature . . . . . . . . . . . . . . . . . . . . . . . .-10c to 125c thermal information thermal resistance (typical, note 1) ja ( c/w) tssop package (note 1) . . . . . . . . . . . . . . . . . . . . 72 maximum operating junction temperature . . . . . . . . . . . . . . . 125 c maximum storage temperature range . . . . . . . . . . . -65 c to 150 c maximum lead temperature (soldering 10s) . . . . . . . . . . . . . 300 c caution: stress above those listed in ?absolute maximum ratings? may cause permanent damage to the device. this is a stress onl y rating and operation of the device at these or any other conditions above those indicated in the operational section of this specification is not implied. note: 1. ja is measured with the component mounted on a low effe ctive thermal conductivity test board in free air. electrical specifications operating conditions: vdd = 5v, t a = -10c to 85c, unless otherwise specified parameter test conditions min typ max units input power supply input supply current, i(vdd) en = 3.3v, dsen# = 0, drsen = 0, pwrch = 0 - 1.4 - ma en = 0v - 1 - a por (power-on reset) threshold v dd rising 4.35 4.45 4.5 v v dd falling 4.05 4.20 4.40 v reference and dac system accuracy percent system deviation fr om programmed vid codes @ 1.356 -0.8 - 0.8 % dac (vid0 - vid5) input low voltage dac programming input low threshold voltage - - 0.3 v dac (vid0 - vid5) input high voltage dac programming input high threshold voltage 0.7 - - v maximum output voltage - 1.708 - v minimum output voltage -0.70 - v channel generator frequency, f sw r fset = 243k, 1% 225 250 275 khz adjustment range guaranteed by design 0.25 - 1.0 mhz error amplifier dc gain -100 - db gain-bandwidth product c l = 20pf - 18 - mhz slew rate c l = 20pf - 4.0 - v/s isen full scale input current -32 - a overcurrent threshold r ocset = 124k - 64 - a soft-start current -31 - a droop current 27 28 30 a gate driver ugate source resistance 500ma source current - 1 1.5 ? ugate source current v ugate-phase = 2.5v - 2 - a isl6217a
4 fn9107.3 june 30, 2005 ugate sink resistance 500ma sink current - 1 1.5 ? ugate sink current v ugate-phase = 2.5v - 2 - a lgate source resistance 500ma source current - 1 1.5 ? lgate source current v lgate = 2.5v - 2 - a lgate sink resistance 500ma sink current - 0.5 0.8 ? lgate sink current v lgate = 2.5v - 4 - a bootstrap diode forward voltage vddp = 5v, forward bias current = 10ma 0.58 0.68 0.76 v power good monitor pgood sense current 2.43 - - ma pgood pull down mosfet r ds(on) (see figure 10) 56 63 82 ? undervoltage threshold (vsen/vref) vsen rising - 85.0 - % undervoltage threshold (vsen/vref) vsen falling - 84.0 - % pgood low output voltage i pgood = 4ma - 0.26 0.4 v logic threshold en, dsen#, drsen low -- 1 v en, dsen#, drsen high 2- - v protection overvoltage threshold (vsen/vref) vsen rising - 112.0 - % delay time delay time from lgate falling to ugate rising vddp = 5v, boot to phase = 5v, ugate - phase = 2.5v, lgate = 2.5v 10 18 30 ns delay time from ugate falling to lgate rising vddp = 5v, boot to phase = 5v, ugate - phase = 2.5v, lgate = 2.5v 10 18 30 ns electrical specifications operating conditions: vdd = 5v, t a = -10c to 85c, unless otherwise specified (continued) parameter test conditions min typ max units isl6217a
5 fn9107.3 june 30, 2005 functional pin description vdd - this pin is used to connect +5v to the ic to supply all power necessary to operate the chip. the ic starts to operate when the voltage on this pin exceeds the rising por threshold and shuts down when the voltage on this pin drops below the falling por threshold. dacout - this pin provides access to the output of the digital-to-analog converter. dsv - the voltage on this pin provides the set point for output voltage during deep sleep mode of operation. fset - a resistor from this pin to ground programs the switching frequency. pwrch - this pin selects the number of power channels. a high logic level on this pin enables 2 channel operation, and a low logic signal enables single channel operation. en - this pin is connected to the system sign al vr_on and provides the enable/disable function for the pwm controller. drsen - this pin connects to system logic ?dprslpvr? and enables deeper sleep mode of operation when a logic high is detected on this pin. dsen# - this pin connects to system logic ?stp_cpu#? and enables deep sleep mode of operation. deep sleep is enabled when a logic low signal is detected on this pin. vid0, vid1, vid2, vi d3, vid4, vid5 - these pins are used as inputs to the 6-bit digital-to-analog converter (dac). vid0 is the least significant bit and vi d5 is the most significant bit. pgood - this pin is used as an input and an output and is tied to the vccp and vcc_mch pgood signals. during start- up, this pin is recognized as an input and prevents further slewing of the output voltage from the ?boot? level until pgood from vccp and vcc_mch is enabled high. after start-up, this pin has an open drain output used to indicate the status of the core output voltage. this pin is pulled low when the system output is outs ide of the regulation limits. pgood includes a timer for power-on delay. ea+ - this pin is connected to the non-inverting input of the error amplifier and is used for setting the ?droop? voltage. comp - this pin provides connection to the error amplifier output. fb - this pin is connected to the inverting input of the error amplifier. soft - this pin programs the slew rate of vid changes, deep sleep and deeper sleep transitions and soft-start after initializing. this pin is connected to ground via a capacitor, and to ea+ through an external ?droop? resistor. vbat - voltage on this pin provides feed-forward battery information which adjusts the oscillator ramp amplitude. isen1, isen2 - these pins are used as current sense inputs from the individual converter channel phase nodes. phase1, phase2 - these pins are connected to the phase nodes of channels 1 and 2, respectively. ug1, ug2 - these pins are the gate-drive outputs to the high side mosfets for channels 1 and 2, respectively. boot1, boot2 - these pins are connected to the bootstrap capacitors, for upper gate-drive, for channels 1 and 2, respectively. vssp1, vssp2 - these pins are connected to the power ground of channels 1 and 2, respectively. lg1, lg2 - these pins are the gate-drive outputs to the low side mosfets for channels 1 and 2, respectively. vddp - this pin provides a low-esr bypass connection to the internal gate drivers for the +5v source. vsen - this pin is used for remote sensing of the microprocessor core voltage. drsv - the voltage on this pin provides the set point for output voltage during deeper sleep mode of operation. ocset - a resistor from this pin to ground sets the overcurrent protection threshold. the current from this pin should be between 10a and 25a (70k ? - 175k ? equivalent) pull-down resistance. stv - the voltage on this pin sets the initial start-up or ?boot? voltage. vss - this pin provides connection for signal ground. isl6217a
6 fn9107.3 june 30, 2005 block diagram i ocset channel power-on reset(por) + - e/a + - pwm pwm pwm1 pwm2 vss vdd fb fs + - clock and vid0 vid1 vid2 vid3 comp generator sawtooth vid4 en 1.3v + - + - + - i droop ocset vid d/a sample hold & current balance isen1 isen2 1.75v vid5 soft vsen pgood ovp + - control and fault logic vbat 1.75v soft start v soft - + 88% rising 84% falling uv v core ref dsv drsv dsen# drsen mux channel current sense high-impedance state 32 count 112% rising 102% falling 32 count clock cycle ea+ dacout stv pwrch pwrch pwrch phase logic phase logic pwm2 pwm1 ug2 phase2 boot2 lg2 lg1 vssp1 vddp ug1 phase1 boot1 vddp vddp vddp vssp2 - + oc clock cycle + high-impedance state isl6217a
7 fn9107.3 june 30, 2005 typical application - 2-phase converter figure 1 shows a 2-phase synchronous buck converter circuit used to provide ?core? voltage regulation for the intel pentium iv mobile processor using imvp-iv? and imvp-iv+? voltage positioning. the isl6217a pwm controller can be configured for two or one channel operation, and the isl6217a can change the number of power channels in operation, dynamically. the number of channels of operation can be changed through the pwrch pin. the isl6217a can be configured for two channel operation in ?act ive? mode and one channel operation in ?deep? and ?deepe r sleep? modes through logic connections to the pwrch pin. the following configuration uses two channel operation in ?active? mode and one channel operation in ?deep? and ?deeper sleep? modes. the circuit shows pin connections for the isl6217a pwm controller in the 38 lead tssop package. figure 1. typical application circuit for isl6217a multiphase pwm controller vdd dacout dsv fset pwrch en drsen dsen# vid0 vid1 vid2 vid3 vid4 vid5 pgood ea+ comp fb soft vbat isen1 phase1 ug1 boot1 vssp1 lg1 vddp lg2 vssp2 boot2 ug2 phase2 isen2 vsen drsv stv ocset vss isl6217a tssop vr_on dprslpvr stp_cpu# vid pwrgd vbattery +5vdc +5vdc +vcc_core isl6217a
8 fn9107.3 june 30, 2005 figure 2. timing diagram showing vr_on, vcc_ core and pgood for vcc_core, vccp and vcc_mch operation initialization once the +5vdc supply voltage, as connected to the isl6217a vdd pin, reaches the power-on reset (por) rising threshold, the pwm drive signals are held in ?high- impedance state? or high impedance mode. this results in both high and low side mosfets being held low. once the supply voltage exceeds the por rising threshold, the controller will respond to a logic level high on the en pin and initiate the soft-start interv al. if the supply voltage drops below the por falling threshold, por shutdown is triggered and the pwm signals are again driven to ?high-impedance state?. the system signal, vr_on is di rectly connected to the en pin of the isl6217a. once the voltage on the en pin rises above 2.0v, the chip is enabled and soft-start begins. the en pin of the isl6217a is also used to reset the isl6217a, for cases when an undervoltage or overcurrent fault condition has latched the ic off. a toggling of the state of this pin to a level below 1.0v will re-enable the ic. for the case of an overvoltage fault, the vdd pin must be reset. during start-up, the isl6217a regulates to the voltage on the stv pin. this is referred to as the ?boot? voltage and is labelled vboot in figure 2. once power good signals are received from the vccp and vcc_mch regulators, the isl6217a will capture the vid code and regulate to this command voltage within 3ms to 12ms. the pgood pin of the isl6217a is both an input and an output and is further described in the ?fault protection? section of this document. soft-start interval once vdd rises above the por rising threshold and the en pin voltage is above the threshold of 2.0v, a soft-start interval is initiated. refer to figure 2 and figure 3. the voltage on the ea+ pin is the reference voltage for the regulator. the voltage on the ea+ pin is equal to the voltage on the soft pin minus the ?droop? resistor voltage, vdroop. during start-up, when the voltage on soft is less than the ?boot? voltage vboot, a small 30a current source, i1, is used to slowly ramp up the voltage on the soft- start capacitor csoft. this slowly ramps up the reference voltage for the controller, and therefore, controls the slew rate of the output voltage. the stv pin is externally programmable and sets the start-up, or ?boot? voltage, vboot. the programming of this voltage level is explained in the ?stv, dsv and drsv? section of this document. the isl6217a pgood pin is bot h an input and an output. the system signal, imvp4_pwrgd, is connected to power good signals from the vccp and vcc_mch supplies. the intersil isl6227, dual voltage regulator is an ideal choice for the vccp and vcc_mch supplies. once the output voltage is within the ?boot? level regulation limits and a logic high pgood signal from the vccp and vccp_mch regulators is received, the isl6217a is enabled to capture the vid code and regulate to that command voltage. refer to figure 2 and figure 3. a second current source, i2, is added to i1, after the initial start-up transition. i2 is approximately 100a, and raises the total soft pin sinking and sourcing current to 130a. this increased current is used to increase the sl ew rate of the reference to v cc-core vid vr_on / en pgood vccp / vcc_mch pgood vcc_core >10us t2 3ms to 12ms v boot v vid < 3ms -12% capture vid code t1 isl6217a
9 fn9107.3 june 30, 2005 meet all active, deep and deeper sleep slew rate requirements of the inte l imvp-iv? and imvp-iv+? specification. figure 3. soft-start tracking circuitry showing internal current sources and "droop" for active, deep and deeper sleep modes of operation the ?droop? current source, i droop, is proportional to load current. this current source is used to reduce the reference voltage on ea+ by the voltage drop across the ?droop? resistor. a more in-depth explanation of ?droop?, and the sizing of this resistor, can be found in the ?droop compensation? section of this document. the choice of value for soft-start capacitor is determined by the maximum slew rate required for the application. an example calculation is shown below. using the combined i1 and i2 current sources on the soft pin as 130a, and the worst case slew rate of (10m v/s), the soft capacitor is calculated as follows: gate-drive signals the isl6217a provides internal gate-drive for a two channel, synchronous buck, core regulator. during two channel mode of operation, the pwm dr ive signals are switched 180 out of phase to reduce ripple current delivered from the dc rail and to the load. the isl6217a was designed with a 4a, low-side gate current sink ability, and a 2a low-side gate current source ability, to efficiently drive the latest, high-performance mosfets. this feature will pr ovide the system designer with flexibility in mosfet select ion, as well as optimum efficiency during active mode of operation. figure 4. channel switching frequency vs r fset pwrch pin a high logic level on this pin enables two channel operation and a low logic signal enables single channel operation. by tying this pin to the stp_cpu# system signal, (dsen# pin on isl6217a) single channel operation will be invoked during the light loading of both deep and deeper sleep. if single channel operation is desired only during deeper sleep, the inversion of system signal dprslpvr can be connected to this pin. the aggressive gate-drive capability and diode emulation of isl6217a, coupled with the sing le channel operation feature results in superior efficiency performance over both light and heavy loads. frequency setting both channel switching frequencies are set up by a resistor from the fset pin to ground. the choice of fset resistance for a desired switching frequency can be approximated using figure 4. the switching frequency is designed to operate between 250khz and 1mhz per phase. core voltage programming the voltage identification pins (vid0, vid1, vid2, vid3, vid4 and vid5) set the dac out put voltage. these pins do not have internal pull-up or pu ll-down capability. these pins will recognize 1.0v, 3.3v, or 5.0v cmos logic. table 1 shows the command voltage, vdac for the 6 bit vid codes. the ic responds to vid code changes as shown in figure 5. pgood is masked between these transitions. c soft soft ea+ r droop isl6217a i 1 i droop + v droop i 2 + error amplifier f 012 . 0 f 013 . 0 mv 10 s 1 a 130 slewrate i c source soft = = = (eq. 1) 0 50 100 150 200 250 250 500 750 1000 channel switching frequency, fsw, (khz) fset resistor value (k ? ) isl6217a
10 fn9107.3 june 30, 2005 table 1. impv-iv vid codes vid5 vid4 vid3 vid2 vid1 vid0 v dac 0000001.708 0000011.692 0000101.676 0000111.660 0001001.644 0001011.628 0001101.612 0001111.596 0010001.580 0010011.564 0010101.548 0010111.532 0011001.516 0011011.500 0011101.484 0011111.468 0100001.452 0100011.436 0100101.420 0100111.404 0101001.388 0101011.372 0101101.356 0101111.340 0110001.324 0110011.308 0110101.292 0110111.276 0111001.260 0111011.244 0111101.228 0111111.212 1000001.196 1000011.180 1000101.164 1000111.148 1001001.132 1001011.116 1001101.100 1001111.084 1010001.068 1010011.052 1010101.036 1010111.020 1011001.004 1011010.988 1011100.972 1011110.956 1100000.940 1100010.924 1100100.908 1100110.892 1101000.876 1101010.860 1101100.844 1101110.828 1110000.812 1110010.796 1110100.780 1110110.764 1111000.748 1111010.732 1111100.716 1111110.700 table 1. impv-iv vid codes (continued) vid5 vid4 vid3 vid2 vid1 vid0 v dac isl6217a
11 fn9107.3 june 30, 2005 active, deep sleep and deeper sleep modes the isl6217a multi-phase controller is designed to control the core output voltage as per the imvp-iv? and imvp-iv+? specifications for active, deep sleep, and deeper sleep modes of operation. after initial start-up, a logic high signal on dsen# and a logic low signal on drsen signals the isl6217a to operate in active mode. refer to table 2. this mode will recognize vid code changes and regulate the output voltage to these command voltages. table 2. output voltage as a function of dsen# and drsen logic states dsen# - stp_cpu# drsen - dprslpvr mode of operation output voltage 1 0 active vid 0 0 deep sleep dsv 0 1 deeper sleep drsv 1 1 deeper sleep drsv figure 5. plot showing timing of vid code changes and core voltage slewing as well as pgood masking figure 6. vcore response for deeper sleep command figure 7. vcore response for deeper sleep command vid[0..5] new vid code current vid code current voltage level new voltage level v cc_core pgood <600ns high vid[0..5] vid code remains the same v cc_core <30us stp_cpu# (dsen#) v deep sleep vid command voltage vid[0..5] vid code remains the same v cc_core stp_cpu# (dsen#) v deeper sleep dprslpvr (drsen) deeper sleep mode short dprslp causes v cc-core to ramp up v deep sleep isl6217a
12 fn9107.3 june 30, 2005 a logic low signal present on stpcpu# (pin dsen#), with a logic low signal on dprslpvr (pin drsen), signals the isl6217a to reduce the core output voltage to the deep sleep level, the voltage on the dsv pin, and to operate in diode emulation. a logic high on dprslpvr, (pin drsen) with a logic low signal on stpcpu# (pin dsen#), signals the isl6217a controller to further reduce t he core output voltage to the deeper sleep level, which is the voltage on the drsv pin. deep sleep and deeper sleep voltage levels are programmable and are explained in the ?stv, dsv and drsv? section of this document. deep sleep enable-dsen# and deeper sleep enable - drsen table 2 shows logic states co ntrolling modes of operation. figure 6 and figure 7 show the timing for transitions entering and exiting deep sleep mode and deeper sleep mode. this is controlled by the syst em signals stpcpu# and dprslpvr. isl6217a pins dsen#, (deep sleep enable #) and drsen, (deeper sleep enable), are connected to these 2 signals, respectively. when dsen# is logic high, and drsen is logic low, the controller will operate in active mode and regulate the output voltage to the vid commanded dac voltage, minus the voltage ?droop? as determined by the load current. voltage ?droop? is the reduction of output voltage proportional to output current. when a logic low is detected at the dsen# and drsen pins, the controller will regulate the output voltage to the voltage seen on the dsv pin minus ?droop?. if the pwrch pin is connected to the dsen# pin then the controller will also switch to single channel operation. when dsen# is logic low and drsen is logic high the controller will operate in d eeper sleep mode. the isl6217a will then regulate to the voltage at the drsv pin minus ?droop?. if the pwrch pin is connected to the dsen# pin, then the controller will also au tomatically switch to single channel operation. if the pwrch pin is connect ed to an inverted dprslpvr system signal, then the controller will automatically switch to single channel operation during deeper sleep mode only. deep and deeper sleep voltage levels are programmable and explained in the ?stv, dsv and drsv? section of this document. stv, dsv and drsv start-up ?boot? voltage - stv the start-up or ?boot? voltage is programmed by an external resistor divider network from the ocset pin. refer to figure 8. internally, a 1.75v reference voltage is output on the ocset pin. the start-up voltage is set through a voltage divider from the 1.75v refer ence at the ocset pin. the voltage on the stv pin will be the voltage the controller will regulate to during the start-up sequence. once the pgood pin of the isl6217a controller is externally enabled high by the vccp and vcc_mch controllers, the isl6217a will then ramp, after a 10s delay, to the voltage commanded by the vid setting minus ?droop?. figure 8. configurations for battery input, overcurrent setting and start, deep sleep and deeper sleep voltage dividers deep sleep voltage - dsv the deep sleep voltage is programmed by an external voltage divider network from the dacout pin. refer to figure 8. the dacout pin is the output of the vid digital-to- analog converter. by having the deep sleep voltage setup from a resistor divider from dac, the deep sleep voltage will be a constant percentage of the vid. through the voltage divider network, deep sleep voltage is set to 98.8% of the programmed vid voltage, as per the imvp-iv? and imvp-iv+? specification. the ic enters the deep sleep mode when the dsen# is low and the drsen pin is low as shown in figure 6 and figure 7. once in deep sleep mode, the controller will regulate to the voltage seen on the dsv pin minus ?droop?. deeper sleep voltage - drsv the deeper sleep voltage, drsv, is programmed by an external voltage divider network from the 1.75v reference on the ocset pin. refer to figure 8. in deeper sleep mode the isl6217a controller will regulate the output voltage to the voltage present on the drsv pin minus ?droop?. this voltage is easily changed by changing the ratio of r 1 , r 2 , and r 3 . the ic enters deeper sleep mode when drsen is high and dsen# is low, as shown in figure 7. isl6217a battery v ref = 1.75v i ocset 36.5k 1.200v 30.1k 0.750v 49.9k ocset stv drsv soft gnd dsv dacout vbat 0.012 f vid command voltage 1.21k 98.8% dacout 98.8k r 1 r 2 r 3 isl6217a
13 fn9107.3 june 30, 2005 overcurrent setting - ocset the isl6217a overcurrent protection essentially compares a user-selectable overcurrent threshold to the scaled and sampled output current. an overcurrent condition is defined when the sampled current is equal to or greater than the threshold current. a step by step process to design for the user-desired overcurrent set point is detailed next. step 1: setting the overcurrent threshold the overcurrent threshold is represented by the dc current flowing out of the ocset pin (see figure 8). since the ocset pin is held at a constant 1.75v, the user need only populate a resistor from this pin to ground to set the desired overcurrent threshold, i ocset . the user should pick a value of i ocset between 10a and 25a. once this is done, use ohm?s law to determine the necessary resistor to place from ocset to ground: for example, if the desired overcurrent threshold is 15a, the total resistance from ocset must equal 117k ? . step 2: selecting isen resistance for desired overcurrent level after choosing the i ocset level, the user must then decide what level of total output current is desired for overcurrent. typically, this number is between 150% and 200% of the maximum operating current of the application. for example, if the max operating current is 46a, and the user chooses 150% overcurrent, the isl6217a will shut down if the output current exceeds 46a*1.5 or 69a. according to the block diagram, the equation below should be used to determine r isen once the overcurrent level, i oc , is chosen. in equation 3, m represents the number of low-side mosfets in one channel, and n represents the number of channels. using the examples above (i oc = 69a, i ocset = 15a) and substituting the values m = 2, n = 2, r ds(on) = 6m ? , r isen is calculated to be 1.5k ? . step 3: thermal compensation for r ds(on) (if desired) if ptcs are used for thermal compensation, then r isen is found using the room temperature value of r ds(on) . if standard resistors are used for risen, then the ?hot? value of r ds(on) should be used for this calculation. mosfet r ds(on) sensing provides advantages in cost, efficiency, and board area. however, if more precise current feedback is desired, a discrete precision current sense resistor, r power , may be inserted between the source of each channels lower mosfet and ground. the small r isen resistor, as described above, is then replaced with a standard 1% resistor and connected from the isen pin of the isl6217a controller to the so urce of the lower mosfet. 3 2 1 ocset ocset r r r i v 75 . 1 r + + = = (eq. 2) 130 a 4 n ) a 2 i ( 2175 . 0 m r i r ocset ) dson ( oc isen ? ? ? + ? ? = (eq. 3) isl6217a
14 fn9107.3 june 30, 2005 battery feed-forward compensation - vbat the isl6217a incorporates battery voltage feed-forward compensation, as shown in figure 8. this compensation provides a constant pulse width modulator gain independent of battery voltage. an understanding of this gain is required for proper loop compensation. the battery voltage is connected directly to the isl6217a by way of the vbat pin, and the gain of th e system ramp modulator is a constant 6.0. fault protection the isl6217a protects the cpu from damaging stress levels. the overcurrent trip point is integral in preventing output shorts of varying degrees from causing current spikes that would damage a cpu. the output overvoltage and undervoltage detection features insure a safe window of operation for the cpu. output voltage monitoring vsen is connected to the local core output voltage and is used for pgood, undervoltage and overvoltage sensing only. refer to the ?block diagram?. the voltage on vsen is compared with two voltage levels which indicate an overvoltage or undervoltage condition of the output. violating either of these conditions results in the pgood pin toggling low to indicate a problem with the output voltage. pgood as previously described, the isl6217a pgood pin operates as both an input and an output. during start-up, the pgood pin operates as an input. refer to figure 10. as per the imvp-iv? and imvp-iv+? specification, once the isl6217a core regulator regulates to the ?boot? voltage, it waits for the pgood logic high signals from the vccp and vcc_mch regulators. the intersil isl6227 is a current sensing comparator pwm 1 circuit + r isen1 + balance error a mplifier comp isen1 v core q 3 q 4 l 02 phase ug1 i l2 isl6217a c out r load v in - q 1 q 2 l 01 phase i l1 v in current sensing comparator pwm 2 circuit ug2 - i a verage + + + - imvp-iv_ r isen2 - - - - + + current a veraging fb r1 r 2 c 1 c 2 v error1 v error2 balance isen2 c dcpl lg2 lg1 ea+ soft r droop c soft + - v rdson v rdson + - i droop v droop + _ reference imvp-iv+_ figure 9. simplified block diagram of the isl6217a voltage and current control loops for a two channel regulator ~ 100ns t q q set clr s r start cpu-up# = uv# and ov# start en rst# 3.3v pgood pgood v ccp 1.2k 10k 3.3v 3ms-12ms t ipgt isl6227 3.3v imvp4 _ pwrgd isl6217 pgood v cc_mch clk_enable# 10k figure 10. internal pgood circuitry for the isl6217a core voltage regulator isl6217a isl6217a
15 fn9107.3 june 30, 2005 perfect choice for these two supplies, as it is a dual regulator and has independent pgood functions for each supply. once these two supplies are within regulation, pgood vccp and pgood vcc_mch will be high impedance, and will allow the pgood of the isl6217a to sink approximately 2.6ma to ground through the internal mosfet, shown in figure 10. the isl6217a detects this current and starts an internal pgood timer. the current sourced into the pgoo d pin is critical for proper start-up operation. the pullup resistor, r pullup is sized to give approximately 2.6ma of current sourced into the pgood pin when the system is enabled and the vccp and vcc_mch supplies are in regulation. as given in the electrical specif ications of this document, the pgood mosfet r ds(on) is given as 82 ? maximum. if 3.3v is used as the supply, then the pullup resistor is given by the following equation: where vsource is the supply minus 5% for tolerance. this will insure that approximately 2.6ma will be sourced into the pgood pin for worst case conditions of low supply and largest mosfet r ds(on) . once the proper level of pgood current is detected, the isl6217a then captures the vid and regulates to this value. the pgood timer is a function of the internal clock and switching frequency. the internal pgood delay can be calculated as follows: the isl6217a controller regulates the core output voltage to the vid command, and once the timer has expired, the pgood output is allowed to go high. note: the pgood functions of the v cc_core , vccp and vcc_mch regulators are wire or?d together to create the system signal ?imvp4_pwrgd?. if any of the supplies fall outside the regulation window, their respective pgood pins are pulled low, which forces imvp4_pwrgd lo w. pgood of the isl6217a is internally disabled during al l vid and mode transitions. overvoltage the vsen voltage is compared with an internal overvoltage protection (ovp) reference, set to 112% of the vid voltage. if the vsen voltage exceeds the ovp reference, a comparator simultaneously sets the ov latch, and pulls the pwm signal low. the drivers turn on the lower mosfets, shunting the converter output to ground. once the output voltage falls below 102% of the set point, the high side and low side mosfets are held off. this prevents dumping of the output capacitors back through the output inductors and lower mosfets, which would cause a negative voltage on the core output. this architecture eliminates the need of a high current, schottky diode on the output. if the overvoltage condition persists, the outputs are cycled between output low and output ?off?, similar to a hysteretic regulator. the ov latch is reset by cycling the vdd supply voltage to initiate a por. depending on the mode of operation, the overvoltage set point is 112% of the vid, deep or deeper sleep set point. undervoltage the vsen pin is also compared to an undervoltage (uv) reference which is set to 84% of the vid, deep or deeper sleep set point, depending on the mode of operation. if the vsen voltage is below the uv reference for mo re than 32 consecutive phase clock cycles, the power good monitor triggers the pgood pin to go low, and latches the chip off until power is reset to the chip, or the en pin is toggled. overcurrent the risen resistor scales the voltage sampled across the lower mosfet and provides current feedback proportional to the output current of each active channel. refer to figure 9. the isen currents from all the active channels are averaged together to form a scaled version of the total output current, i average . i average is compared with an internally generated overcurrent trip threshold, which is proportional to the current sourced from the ocset pin, i ocset . the overcurrent trip current source is programmable and described in the ?overcurrent setting - ocset? section of this document. if i average exceeds the i ocset level, an up/down counter is enabled. if i average does not fall below i ocset within 32 phase cycle counts, the pgood pin transitions low and latches the chip off. if normal operation resumes within the 32 phase cycle count window, the controller will continue to operate normally. refer to the ?block diagram?. note: due to ?droop? there is inherent current limit, since load current cannot exceed the amount that would command an output voltage lower than 84% of the vid voltage. this would result in an undervoltage shutdown, and would also cause the pgood pin to transition low and latch the chip off. control loops the ?block diagram? and figure 9 shows a simplified diagram of the voltage regulation and current control loops for a two-phase converter. both voltage and current feedback are used to precisely regulate voltage and tightly control output currents, i l1 and i l2 , of the two power channels. the voltage loop is comprised of the error amplifier, comparators, internal gate drivers, and mosfets. the error amplifier drives the modulator to force the fb pin to the imvp-iv? and imvp-iv+? reference minus ?droop?. () () ? ? ? = ? = k 2 . 1 82 ma 6 . 2 3 . 3 05 . 0 3 . 3 max r ma 6 . 2 vsource r dson pullup (eq. 4) timer delay = 3072 / fsw (eq. 5) isl6217a
16 fn9107.3 june 30, 2005 voltage loop the output core voltage feedback is applied to the error amplifier through the compensation network. the signal seen on the fb pin will drive the error amplifier output either high or low, depending on the core voltage. a core voltage level that is lower than the imvp-iv? and imvp-iv+? reference, as output from the 6 bit dac, makes the amplifier output move towards a higher output voltage level. the amplifier output voltage is applied to the positive inputs of the comparators by the balance summing networks. out-of-phase sawtooth signals are applied to the two comparator inverting inputs. increasing error amplifier voltage results in increased comparator output duty cycle. this increased duty cycle signal is passed through the pwm circuit to the internal gate-drive circuitry. the output of the internal gate-drive is directly connected to the gate of the mosfets. increased duty cycle or on-time for the high side mosfet transistors results in increased output voltage, vcore, to compensate for the low output voltage sensed. current loop the current control loop keeps the channel currents in balance. during the pwm off-time of each channel, the voltage vr ds(on) , developed across the lower mosfet is sampled. internally, the isen pin is held at virtual ground during this interval, and vr ds(on) is impressed across the r isen resistor. this provides current feedback proportional to the output current of each channel. the scaled output currents from all active channels are combined to create an average current reference i average , proportional to the converter total output current. this signal is then subtracted from the individual channel scaled output currents to produce a current correction signal for each channel. the current correction signal keeps each channel output current contribution balanced relative to the other active channels. each current correction signal is subtracted from the error amplifier output and fed to the individual channel pwm circuits. for example, assume the voltage sampled across q4 in figure 9 is higher than that sampled across q2. the isen2 current would be higher than isen1. when the two reference currents are averaged, they accurately represent the total output current of the converter. the reference current i average is then subtracted from the isen currents. this results in a positive offset for channel 2 and a negative offset for channel 1. these offsets are subtracted from the error amplifier signal and perform phase balance correction. the v error2 signal is reduced, while v error1 would be increased. the pwm circuit would then reduce the pulse width to lower the output current contribution by channel 2, while doing the opposite to channel 1, thereby balancing channel currents. droop compensation microprocessors and other peripherals tend to change their load current demands from near no-load to full load often during operation. these same devices require minimal output voltage deviation during a load step. a high di/dt load step will cause an output voltage spike. the amplitude of the spike is dictated by the output capacitor esr, multiplied by the load step magnitude, plus the output capacitor esl, times the load step di/dt. a positive load step produces a negative output voltage spike and vice versa. a large number of low-series-impedance capacitors are often used to prevent the output voltage deviation from exceeding the tolerance of some devices. one widely accepted solution to this problem is output voltage ?droop?, or active voltage positioning. as shown in figure 3 and figure 9, the average channel current is used to control the ?droop? current source, i droop . the ?droop? current source is a controlled current source and is proportional to output current. this current source is approximately 87% of the averaged isen currents. the droop current is sourced out of the soft pin through the droop resistor and returns through the ea+ pin. this creates a ?droop? voltage v droop , which subtracts from the imvp- iv? and imvp-iv+? reference voltage on soft to generate the voltage set point for the core regulator. full load current for the intel imvp-iv? and imvp-iv+? specification is 32a. knowing that the droop current, sourced out of the soft pin, will be 87% of the isen averaged currents, a ?droop? resistor r droop , can be selected to provide the amount of voltage ?droop? required at full load. the selection of this resistor is explained in the following section. selection of rdroop figure 11 shows a static ?droop? load line for the 1.484v active mode. the isl6217a, as previously mentioned, allows the programming of the load line slope by the selection of the rdroop resistor. as per the intel imvp-iv? and imvp-iv+? specification, droop = 0.003 ( ? ). therefore, 25a of full load current equates to a 0.075v droop output voltage from the vid setpoint. refer to figure 3 and figure 9, r droop can be v out,hi v out,lo i out,max i out,nl v out,nom i out,mid -3 m _ load line (25a,1.409v ) (0a,1.506v) (0a,1.484v) (25a,1.431v ) (0a,1.462v) (25a,1.387v ) static tolerance bands nominal "droop" load line figure 11. imvp-iv active mode static load line isl6217a
17 fn9107.3 june 30, 2005 selected based on r isen which is calculated through equation 3, r ds(on) , and droop as per the block diagram or the following equation: diode emulation diode emulation allows for higher converter efficiency under light-load situations. with diode emulation active, the isl6217a will detect the zero current crossing of the output inductor and turn off lgate. this ensures that discontinuous conduction mode (dcm) is achieved. in dcm, conduction losses are reduced in the low-side mosfet, consequently boosting efficiency. the isl6217a operates in dcm in both deep and deeper sleep mode. adaptive shoot-through protection both drivers incorporate adaptive shoot-through protection to prevent upper and lower mosfets from conducting simultaneously and shorting the input supply. this is accomplished by ensuring the falling gate has turned off one mosfet before the other is allowed to turn on. during turn-off of the lower mosfet, the lgate voltage is monitored until it reaches a 1v threshold, at which time the ugate is released to rise. adaptive shoot-through circuitry monitors the upper mosfet gate-to-source voltage during ugate turn-off. once the upper mosfet gate-to-source voltage has dropped below a threshold of 1v, the lgate is allowed to rise. component selection guidelines output capacitor selection output capacitors are required to filter the output inductor current ripple and supply the transient load current. the filtering requirements are a function of the channel switching frequency and the output ripple current. the load transient requirements are a function of the slew rate (di/dt) and the magnitude of the transient load current. the microprocessor used for imvp-iv? and imvp-iv+? will produce transient load rates as high as 30a/ns. high frequency, ceramic capacitors are used to supply the initial transient current and slow the rate-of-change seen by the bulk capacitors. bulk filter capacitor values are generally determined by the esr (effective series resistance) and voltage rating requirements rather than actual capacitance requirements. to meet the stringent requirements of imvp-iv? and imvp-iv+?, (15) 2.2f, 0612 ?flip chip? high frequency, ceramic capacitors are placed very close the processor power pins, with care being taken not to add inductance in the circuit board traces that could cancel the usefulness of these low inductance components. specialized low-esr capacitors, intended for switching regulator applications, are recommended for the bulk capacitors. the bulk capacitor esr and esl determine the output ripple voltage and the initial voltage drop following a high slew-rate transient edge. recommended are at least (4) 4v, 220f sanyo sp-cap capacitors in parallel, or (5) 330f sp-cap style capacitors. thes e capacitors provide an equivalent esr of less than 3m ? . these components should be laid out very close to the load. as the sense trace for vsen may be long and routed close to switching nodes, a 1.0f ceramic decoupling capacitor is located between vsen and ground at the isl6217a. output inductor selection the output inductor is selected to meet the voltage ripple requirements and minimize the converter response time to a load transient. in a multi-phase converter topology, the ripple current of one active channel partially cancels with the other active channels to reduce the overall ripple current. the reduction in total output ripple current results in a lower overall output voltage ripple. the inductor selected for the power channels determines the channel ripple current. increasing the value of inductance reduces the total output ripple current and total output voltage ripple; however, increasing the inductance value will slow the converter response time to a load transient. one of the parameters limiting the converter response time to a load transient is the time required to slew the inductor current from its initial current level to the transient current level. during this interval, the difference between the two levels must be supplied by the output capacitance. minimizing the response time can minimize the output capacitance required. the channel ripple can be reasonably approximated by the following equation: the total output ripple current can be approximated from the curves in figure 10. they provide the total ripple current as a function of duty cycle and number of active ch annels, norma lized to the parameter k norm at zero duty cycle, where l is the channel inductor value. () ) ( m r r droop 3 . 2 r ) dson ( isen droop ? ? ? = (eq. 6) in out sw out in ch v v l f v v i ? ? ? = ? (eq. 7) sw out norm f l v k ? = (eq. 8) isl6217a
18 fn9107.3 june 30, 2005 figure 12. output ripple current multiplier vs duty cycle find the intersection of the active channel curve and duty cycle for your particular application. the resulting ripple current multiplier from the y-axis is then multiplied by the normalization factor k norm , to determine the total output ripple current for the given application. find the intersection of the active channel curve and duty cycle for your particular application. the resulting ripple current multiplier from the y- axis is then multiplied by the normalization factor k norm , to determine the total output ripple current for the given application. input capacitor selection use a mix of input bypass capacitors to control the voltage overshoot across the mosfets. use ceramic capacitors for the high frequency decoupling, and bulk capacitors to supply the rms current. small ceramic capacitors must be placed very close to the upper mosfet to suppress the voltage induced in the parasitic circuit impedances. two important parameters to consider when selecting the bulk input capacitor are the voltage rating and the rms current rating. for reliable operation, select a bulk capacitor with voltage, and current ratings above the maximum input voltage and the largest rms current required by the circuit. the capacitor voltage rating should be at least 1.25 times greater than the maximum input voltage and a voltage rating of 1.5 times is a conservative guideline. the rms current requirement for a converter design can be approximated with the aid of figure 13. follow the curve for the number of active channels in the converter design. next determine the worst case duty cycle for the converter and find the intersection of this value and the active channel curve. the worst case duty cycle is defined as the maximum operating core output voltage divided by the minimum operating battery voltage. find the corresponding y-axis value, which is the current multiplier. multiply the total full load output current, not the channel value, by the current multiplier value found, and the result is the rms input current which must be supported by the input capacitors. figure 13. input rms ripple current multiplier mosfet selection and considerations for the intel imvp-iv? and imvp-iv+? application, which requires up to 25a of current, it is suggested that 2 channel operation with (3) mosfets per channel be implemented. this configuration would be: (1) high switching frequency, low gate charge mosfet for the upper, and (2) low r ds(on) mosfets for the lowers. in high-current pwm applications, the mosfet power dissipation, package selection and heatsink are the dominant design factors. the power dissipation includes two loss components: conduction loss and switching loss. these losses are distributed between the upper and lower mosfets according to duty cycle of the converter. refer to the pupper and plower equations below. the conduction losses are the main component of power dissipation for the lower mosfets. only the upper mosfets have significant switching losses, since the lower devices turn on and off into near zero voltage. the following equations assume linear voltage-current transitions and do not model power loss due to the reverse-recovery of the lower mosfets body diode. the gate-charge losses are dissipated in the isl6217a drivers and do not heat the mosfets; however, large gate-charge increases the switching time t sw, which increases the upper mosfet switching losses. ensure that both mosfets are within their maximum junction temperature, at high ambient temperature, by calculating the temperature rise according to package thermal-resistance specifications. cm norm total k k i ? = ? (eq. 9) () () in out in on ds 2 o lower v v v r i p ? = (eq. 10) isl6217a
19 fn9107.3 june 30, 2005 typical application - 2 phase converter using isl6217a pwm cont roller - 38 lead tssop figure 14 shows the isl6217a, synchronous buck converter circuit used to provide the core voltage regulation for the intel imvp-iv? and imvp-iv+? application. the circuit uses 2 channels for delivering up to 25a steady state current, and has a 250khz channel switching frequency. this circuit also switches to single channel operation for deep and deeper sleep modes of operation. for thermal compensation, ptc resistors are used as sense resistors. the ou tput capacitance is less than 3m ? of esr, and are (4) 220f, 4v sp-cap parts in parallel with (35) high frequency, 10f ceramic capacitors. figure 14. typical application circuit for the im vp-iv? and imvp-iv+? core voltage regulator () 2 f t v i v v r i p sw sw in o in out on ds 2 o upper + = (eq. 11) a nalog gnd power gnd vdd dacout dsv fset pwrch en drsen dsen# vid0 vid1 vid2 vid3 vid4 vid5 pgood ea+ comp fb soft vbat isen1 phase1 ug1 boot1 vssp1 lg1 vddp lg2 vssp2 boot2 ug2 phase2 isen2 vsen drsv stv ocset vss isl6217a tssop 4 x 220 f & 35 x 10 f 2 x si4404dy 2 x si4404dy 0.8 h 1 x irf7811w 1 x irf7811w 0.8 h 4 x 10 f vr_on dprslpvr dpslp# vid mvp4_pgood vbattery +5vdc +5vdc +vcc_core 36.5k_1% 30.1k_1% 49.9k_1% 4 x 10 f 1.5k_1%ptc 1.5k_1%ptc 3.57k_1% 13k_1% 2200pf 3.40k_1% 1 f 98.8k_1% 1.20k_1% 243k_1% 4.7 f 1800pf no-pop no-pop 560pf 10_1% 0.33 f 1r5_5% 0.33 f 10_1% 0.027 bat54 bat54 0.012 etq-p3h0r8ba etq-p3h0r8ba 1r5_5% isl6217a
20 all intersil u.s. products are manufactured, assemb led and tested utilizing iso9000 quality systems. intersil corporation?s quality certifications can be viewed at www.intersil.com/design/quality intersil products are sold by description only. intersil corpor ation reserves the right to make changes in circuit design, soft ware and/or specifications at any time without notice. accordingly, the reader is cautioned to verify that data sheets are current before placing orders. information furnishe d by intersil is believed to be accurate and reliable. however, no responsibility is assumed by intersil or its subsidiaries for its use; nor for any infringements of paten ts or other rights of third parties which may result from its use. no license is granted by implication or otherwise under any patent or patent rights of intersil or its subsidiari es. for information regarding intersil corporation and its products, see www.intersil.com fn9107.3 june 30, 2005 isl6217a thin shrink small outlin e plastic packages (tssop) index area e1 d n 123 -b- 0.10(0.004) c a m bs e -a- b m -c- a1 a seating plane 0.10(0.004) c e 0.25(0.010) b m m l 0.25 0.010 gauge plane a2 notes: 1. these package dimensions are wi thin allowable dimensions of jedec mo-153-bd-1, issue f. 2. dimensioning and tolerancing per ansi y14.5m - 1982. 3. dimension ?d? does not include mold flash, protrusions or gate burrs. mold flash, protrusion and gate burrs shall not exceed 0.15mm (0.006 inch) per side. 4. dimension ?e1? does not include in terlead flash or protrusions. inter- lead flash and protrusions shall not exceed 0.15mm (0.006 inch) per side. 5. the chamfer on the body is optional. if it is not present, a visual index feature must be located within the crosshatched area. 6. ?l? is the length of terminal for soldering to a substrate. 7. ?n? is the number of terminal positions. 8. terminal numbers are shown for reference only. 9. dimension ?b? does not include dam bar protrusion. allowable dambar protrusion shall be 0.08mm (0.003 inch) total in excess of ?b? dimen- sion at maximum material conditi on. minimum space between protru- sion and adjacent lead is 0.07mm (0.0027 inch). 10. controlling dimension: millimete r. converted inch dimensions are not necessarily exact. (angles in degrees) 0.05(0.002) m38.173 38 lead thin shrink small outline plastic package (compliant to jedec mo-153-bd-1 issue f) symbol inches millimeters notes min max min max a - 0.047 - 1.20 - a1 0.002 0.006 0.05 0.15 - a2 0.031 0.051 0.80 1.05 - b 0.0075 0.0106 0.17 0.27 9 c 0.0035 0.0079 0.09 0.20 - d 0.378 0.386 9.60 9.80 3 e1 0.169 0.177 4.30 4.50 4 e 0.0197 bsc 0.500 bsc - e 0.246 0.256 6.25 6.50 - l 0.0177 0.0295 0.45 0.75 6 n38 387 0 8 0 8 - rev. 0 1/03

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